The present invention relates to a television receiver which decodes video signals for a plurality of broadcast standards, such as MUSE (multiple sub-Nyquist sampling encoding) standard to transmit a HighVision signal and EDTV-2 (second generation extended definition television) standard.
In recent years, HighVision broadcast has been put in practical use and broadcast employing a MUSE standard was commenced. In NTSC standard broadcast, broadcast employing an EDTV-2 standard is going to be commenced and television receivers which can receive video signals of a plurality of broadcast standards are increasingly needed.
A decoder for a MUSE standard is introduced in a technical report "MUSE HighVision transmission standard" by Ninomiya edited by Electronic Information Communication Institute and a decoder for an EDTV-2 standard is introduced in "Part 2, transmission and reception circuits--high resolution component is separately transmitted", Nikkei Electronics 1994, January 31 vol. 600, pp. 142-149.
Examples of a block diagram generally thought as a decoder part of a television receiver which can receive a plurality of kinds of broadcast standards are shown in FIGS. 8 and 9. In exemplary embodiments of the present invention, a case having two video signal processing blocks as a plurality of video signal processing means and three channels for each MUSE standard and NTSC standard as the number of video signal sources is described for simplicity of explanation.
FIG. 8 is an example of a block diagram of a decoder part of a television receiver for receiving multi-standards to be generally thought in accordance with the prior art.
In FIG. 8, the terminals 1, 2 and 3 are video signal input terminals for a MUSE standard signal. The block 4 is a selector circuit for selecting a video signal out of a plurality of input terminals 1, 2 and 3. The block 5 is an A/D (from analog to digital) converter for converting an analog video signal oitputted from selector circuit 4 into a digital video signal. The block 6 is a first video signal processing block for decoding an output signal of A/D converter 5. The block 120 is a first memory block for storing a video signal during several frame periods and is connected to first video signal processing block 6. The block 126 is a D/A (from digital to analog) converter for converting a digital video signal outputted from first video signal processing block 6 into an analog video signal.
The terminals 11, 12 and 13 are video signal input terminals for an EDTV-2 standard signal. The block 14 is a selector circuit for selecting a video signal out of a plurality of input terminals 11, 12 and 13. The block 15 is an A/D converter for converting an analog output signal of selector circuit 14 into a digital signal. The block 16 is a second video signal processing block for decoding an output signal of A/D converter 15. The block 220 is a second memory block for storing a video signal during several frame periods and is connected to second video signal processing block 16. The block 226 is a D/A converter for converting an output signal of second video signal processing block 16 into an analog signal.
The block 25 is a selector circuit for selecting an output signal of either D/A converter 126 or 226. The terminal 27 is an output terminal of selector circuit 25. The block 21 is a selection control circuit for controlling selection of selection circuits 4, 14 and 25.
The function of a decoding part of television receiver for receiving multi-standards configured like the above in accordance with the prior art is explained below.
In the case in which a video signal of MUSE standard is displayed, a selection control circuit 21 controls selector circuit 25 so as to select an output of D/A converter 126 and selects an input signal by controlling a selector circuit 4. For example, when a satellite broadcast (BS, hereafter) is received, an input terminal 1 connected to a detector output terminal of a BS tuner is selected and when a laser disk picture is watched, an input terminal 2 connected to an external input terminal is selected.
The inputted video signal is decoded at a first video signal processing block 6 after being converted into a digital signal at an A/D converter 5. The first video signal processing block 6 is composed of a moving picture processing block for executing interpolation processing from an input signal during continuous several horizontal scanning periods, a still-picture processing block for executing interpolation processing from a signal during two frame periods stored in first memory block 120, a movement detecting block for detecting a moving part from the signal during the two frame periods and a block for mixing an output signal of the moving picture processing block and an output signal of the still picture processing block and outputs a signal in which its mixing ratio is varied according to a signal expressing a degree of movement supplied from the movement detecting block. Thus, a video signal of MUSE system is decoded.
In the case in which a video signal of EDTV-2 standard is displayed, selection control circuit 21 controls selector circuit 25 so as to select an output of D/A converter 226 and selects an input signal by controlling selector circuit 14. For example, when an EDTV-2 broadcast is received, an input terminal 11 connected to a detector output terminal of a tuner is selected and when a laser disk picture or a video cassette picture is watched, input terminal 12 connected to an external input terminal is selected.
The inputted video signal is decoded at second video signal processing block 16 after being converted into a digital signal at A/D converter 15. At second video signal processing block 16, a composite video signal is separated into a luminance signal and a chrominance signal (that is, Y/C separation) by three dimensional processing and an enhanced signal multiplexed on the luminance signal is decoded and reproduced to increase vertical and horizontal resolution are increased. In this case, a high frequency component to be superimposed is controlled by a movement signal detected from a frame difference signal. Thus, a video signal of EDTV-2 standard is decoded. In the example shown in FIG. 8, memory blocks 120 and 220 are used for a MUSE standard signal and an EDTV-2 standard signal, respectively and the memory block is not used in common.
FIG. 9 is another example of a block diagram of a decoder part of a television receiver for receiving multi-standards to be generally thought in accordance with the prior art.
In FIG. 9, the terminals 1, 2 and 3 are video signal input terminals for MUSE standard. The block 4 is a selector circuit for selecting a video signal out of a plurality of input terminals 1, 2 and 3. The block 5 is an A/D converter for converting an analog output signal of selector circuit 4 into a digital signal. The block 6 is a first video signal processing block for decoding an output signal of A/D converter 5. The block 126 is a D/A converter for converting an output signal of first video signal processing block 6 into an analog signal.
The terminals 11, 12 and 13 are video signal input terminals for EDTV-2 standard. The block 14 is a selector circuit for selecting a video signal out of a plurality of input terminals 11, 12 and 13. The block 15 is an A/D converter for converting an analog output signal of selector circuit 14 into a digital signal. The block 16 is a second video signal processing block for decoding an output signal of A/D converter 15. The block 226 is a D/A converter for converting an output signal of second video signal processing block 16 into an analog signal.
The block 25 is a selector circuit for selecting an output signal of either D/A converter 126 or 226. The block 20 is a memory block for storing a video signal during several frame periods and is connected to first video signal processing block 6. The block 23 is a tristate buffer through which an output signal of first video signal processing block 6 is supplied to memory block 20. The block 24 is a tristate buffer through which an output signal of second video signal processing block 16 is supplied to memory block 20. The block 21 is a selection control circuit for controlling selection of selection circuits 4, 14 and 25 and tristate buffers 23 and 24.
The function of a decoder part of a television receiver for receiving multi-standards configured like the above in accordance with the prior art is explained below.
The basic function is similar to that of the previous example shown in FIG. 8. The difference from that shown in FIG. 8 is that a memory block 20 used at video signal decoding of each standards is used in common and this point is an improved point from the previous example.
In the case in which a video signal of MUSE standard is decoded, tristate buffer 23 is controlled to be in a normal output state and tristate buffer 24 is controlled so as to be in a high impedance state. This control is made by an output signal of selection control circuit 21.
In the case in which a video signal of EDTV-2 standard is decoded, tristate buffer 23 is controlled to be in a high impedance state and tristate buffer 24 is controlled so as to be in a normal output state.
In the above-described configuration shown in FIG. 9, however, when a video signal processing block 6 or 16 is selected by a selection control circuit 21, because a control signal wire from selection control circuit 21 to video signal processing blocks 6 and 16 is common, the video signal processing blocks 6 and 16 are transiently in a simultaneous output state during some period, a signal of the output terminal of either video signal processing block flows into the output terminal of the other video signal processing block due to such as drive ability difference between the output terminals of the video signal processing blocks and drive elements at the above-mentioned output terminals could be broken.
Further, because power is supplied to also the video signal processing block which is not used now, wasteful power is dissipated.
In the case in which it is tried to decrease power dissipation by stopping a drive clock signal of the video signal processing block which is not used now, there is a problem that it takes long time to output a video signal because the action starts from a sync detection at selecting a video signal processing block.
In the case in which the memory block used in common is controlled by only a selection control signal of the input or output signal, there is a problem that a normal selection is impossible when a plurality of different standards exist in the same channel.